1. Field of the Invention
The present invention relates to a circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages which may occur, for example, as a consequence of static charges.
2. Description of the Prior Art
In integrated MOS circuits, voltages having magnitudes in the kV range can arise at the inputs thereof as a result of static charges. These high voltages lead to a destruction of the oxide of the circuits, for example of the gate oxide of the input transistors. The breakdown voltages in this connection are in the order of magnitude of 60 V.
It is known, in principle, to provide bypass circuits at the inputs of integrated MOS circuits in order to avoid destructions which may result as a consequence of excessively high voltages.